The disclosure below relates to current-mode bus line drivers and to methods of achieving relatively constant current output such bus line drivers.
Current-mode signaling is ideal for certain situations, such as a bus-based signaling environment. When using current-mode signaling in this environment, an active driver device alternately drives either a high current or a low current on the bus. The current passes through the impedance of the bus line and any termination resistance, thereby producing corresponding voltages on the bus line. Generally, only one driver is active at any given time, and presents a high impedance to the bus when it is not active. However, drivers used in high-speed bus lines are sometime active during overlapping times to enable higher signaling rates.
FIGS. 1-4 illustrate one bus design where two devices might be concurrently active. In this design, there is a single bus line 20 having a fixed impedance. In this example, the bus line impedance is 28 ohms. The bus is terminated at one end with a termination resistance Rterm which is approximately equal to the bus line impedance of 28 ohms. This end of the bus line is referred to herein as the distal end. The bus is biased by a termination voltage Vterm, which in this example is equal to 1.8 V.
A plurality of driver devices 22-25 are connected to alternately drive bus line 20. In addition, a signal receiving device 26 is connected to receive and interpret bus line signals resulting from the activities of driver devices 22-25. The signal receiving device is located at a first or proximal end of the bus line in this example. The signal receiving device presents a high impedance to the bus line.
FIGS. 2-4 illustrate waveforms that result when driver device 23 transitions from a xe2x80x9chighxe2x80x9d bus line voltage to a xe2x80x9clowxe2x80x9d bus line voltage. In this example, the high bus voltage Vhi is equal to 1.8 volts, and the low bus voltage Vlo, is equal to 1.0 volts. To produce Vhi on the bus, driver device 23 supplies no current to the bus. To produce Vlo, driver device 23 sinks 30 mA.
FIG. 2 shows the current waveform at driver device 23 as it transitions from Vhi to Vlo. Initially, the current is zero, resulting in a bus voltage of Vhi. When driver device 23 switches to produce a xe2x80x9clowxe2x80x9d bus voltage of Vlo, the current through the driver device is xe2x88x9230 mA.
FIG. 3 shows the resulting voltage waveform at driver device 23. Initially, at the transition of driver device 23 from 0 to 30 mA, driver device 23 sees an impedance of 28 ohms in each bus line direction. These two impedances are seen in parallel, so the overall impedance is equal to 1/(1/28+1/28) or 14 ohms. The voltage drop across this impedance is equal to impedance multiplied by current, or xe2x88x9230 mAxc3x9714 ohms (about xe2x88x92400 mV). The bus line is biased at its distal end by 1.8 V, so the resulting voltage at driver device 23 is 1.8 Vxe2x88x92400 mV=1.4 V. This voltage level (1.4 V) is referred to as intermediate voltage Vint in FIG. 3. Generally, Vint is equal to (Vhi+Vlo)/2.
This 400 mV voltage signal propagates in each direction on the bus line, at a finite velocity. When the signal gets to the distal end of the bus line, it encounters the matched impedance of Rterm, and there is no signal reflection. When the signal gets to the proximal end of the bus, however, it encounters the infinite input impedance of signal receiving device 26. This causes a voltage reflection, creating a return voltage wave whose amplitude is equal to the voltage of the original xe2x88x92400 mV signal. This voltage subtracts from the existing bus line voltage of 1.4 V, to result in a bus line voltage of Vlo, or 1.0 V in the illustrated example. FIG. 4 shows the resulting voltage waveform at signal receiving device 26. The signal receiving device sees a single transition from Vhi to Vlo, delayed in time by the propagation delay from driver device 23 to signal receiving device 26.
This second xe2x88x92400 mV signal propagates all the way back to the distal end of the bus line. When the second reflection reaches driver device 23, the driver device sees the full 800 mV signal. This 800 mV signal continues back towards Rterm, which absorbs the signal and eliminates any further reflections. FIG. 3 shows the arrival of this second signal or wavefront at driver device 23, at which time the voltage becomes equal to Vlo.
At this point, the circuit has reached a steady state voltage of Vlo, (1.0 V) and no steady-state current flows through the proximal end of the signal line. As a result, the total bus line impedance seen by driver device 23 is now the impedance of the distal side of the bus line: 28 ohms. This is what produces the steady-state output voltage of 1.0 V: Vtermxe2x88x9230 mAxc3x97Rbus=1.0 V.
When it is desired to operate the bus line at the highest possible speeds, subsequent signal transitions are introduced on the bus line before the signal from the earlier transitions have reached their final, steady state. Although this creates complex waveforms at the driving devices, the signal at the signal receiving device remains relatively simple, so that the signal receiving device can interpret the signal by differentiating only between two signal voltages: Vhi and Vlo.
However, the situation becomes slightly more complicated in the case of so-called xe2x80x9cback-to-backxe2x80x9d reads from driver devices. A back-to-back read is when a first driver device produces a signal that is immediately followed by a signal from a second driver device. Because of signal propagation delays, this has the potential of creating signal glitches, sometimes referred to as xe2x80x9cwired-OR glitches.xe2x80x9d
Consider the example shown in FIG. 5 where the bus configuration includes a signal receiving device 40, a first and proximal driver device 41, and a second and distal driver device 42. In this example, td represents the signal propagation delay between distal driver device 42 and proximal driver device 41. The symbol tr represents the signal propagation delay between proximal driver device 41 and signal receiving device 40.
Assume that proximal driver device 41 produces a low voltage signal, which is immediately followed by a low voltage signal from device driver 42. One way to accomplish this is to turn off proximal driver device 41 simultaneously with turning on driver device 42. Because of signal propagation delays, however, this would result in a voltage glitch at signal receiving device 40: the terminating signal from device 41 would reach signal receiving device 40 before the new signal from device 42 arrived. In other words, it would appear that the bus was not being driven for some short period of time.
While a glitch such as this could perhaps be accommodated, doing so would not utilize the full bandwidth of the bus line. To utilize the full bandwidth, distal driver device 42 is turned on for some time prior to turning off proximal driver device 41, so that its signal reaches signal receiving device 40 at the same time as the trailing edge of the signal from proximal driver device 41.
FIGS. 6-8 illustrate this sequence. FIG. 6 shows the current waveforms at distal driver device 41 and proximal driver device 42, respectively. At point A, the distal driver device 42 is turned on and begins sinking 30 mA. At a later time B, the proximal driver device 42 is turned off and stops sinking current. The time from A to B is equal to td.
FIG. 7 shows the resulting voltage at distal driver device 42. At point A, when distal driver device 42 is turned on, the bus is presented with an additional current of 30 mA. Initially, this current sees an effective resistance of 14 ohms. The additional voltage drop caused by this current is equal to the original bus line voltage of 400 mV. The total voltage drop on the bus signal line is the sum of the voltage drop caused by proximal driver device 41 and the voltage drop caused by distal driver device 42: 800 mV+400 mV=1200 mV. Since the bus is terminated at 1.8 volts, the resulting bus line voltage is 1.8 Vxe2x88x921.2 V=600 mV. This bus line voltage is referred to as Vtemp in FIG. 7.
The Vtemp signal propagates toward proximal driver device 41 and signal receiving device 40. When it reaches proximal driver device 41 at point A, proximal driver device 41 is turned off. FIG. 8 shows the resulting voltage waveforms at proximal driver device 41 and at receiving device 40. The voltage at these points remains at a constant Vlo (1.0 V) at both of these devices, which is the desired result.
This Vlo signal reaches distal driver 42 at point C, illustrated in FIG. 7, at which time the voltage at distal driver 42 returns to Vlo.
The operation illustrated by FIGS. 6-8 assumes that the distal driver device 42 is able to supply a constant current to bus line 45. In many cases, however, this is difficult to accomplish. This is because of the current/voltage characteristics of the MOS current driver transistors used in many circuits of this type.
FIG. 9 shows an open-drain NMOS transistor current source 45 as used in many prior art current-mode drivers. The gate of transistor 45 is connected to a constant voltage VG. The source is tied to a low voltage (usually the chip ground Vss), and the drain is connected to the bus line. Current drawn through the transistor is also drawn through the bus line, which in turn lowers the voltage VO of the bus line.
FIG. 10 shows the current/voltage characteristics of a MOS transistor at a given gate voltage VG. At drain output voltages VO that are above a pinch-off or threshold voltage VDSAT (in this example equal to about 1.0 V), the current output lout is somewhat constant with varying output voltages. Below VDSAT, however, the output current falls quickly. At VO=600 mV, IOut falls from the desired 30 mA to as much as 15% below that value.
FIG. 11 shows the result at receiving device 40 of this drop in output current, in the back-to-back read example discussed above with reference to FIGS. 7-9. Assume that distal driver device 42 is able to supply a current of 25 mA at the reduced voltage Vtemp (shown in FIG. 7). This produces an initial voltage drop of 25 mAxc3x9714 ohms: about 350 mV. This drop is in addition to the 400 mV drop already being created by proximal driver device 41. The front of the resultant wave propagates toward controller 40 along with the trailing edge of the signal from proximal driver device 41. When the 350 mV wave reaches controller 40 (after a delay of td+tr), a reflection doubles the value of the voltage drop from 350 mV to 700 mV. Thus, the voltage at controller 40 is initially 1.0 V, but then rises to 1.1 voltsxe2x80x94a 10% increase over the nominal low input voltage of controller 40, and a 30% increase relative to the nominal high/low input margin of signal receiving device 40. This higher voltage, referred to in FIG. 10 as Vglitch, persists until the wave propagates back to distal driver device 42, at which time this device sees an increased line impedance of 28 ohms (and a higher corresponding line voltage) and begins to output more current. A second wave is then created and propagated toward controller 40. When this wave reaches controller 40 (after another delay of td+tr), the voltage at controller 40 will regain its steady-state voltage of 1.0 V.
Although FIG. 11 illustrates a back-to-back read operation involving two adjacent xe2x80x9clows,xe2x80x9d other transitions produce analogous results. Also, it should be noted that FIGS. 7 and 11 have been simplified by disregarding the effects of xe2x80x9cvoltage doublingxe2x80x9d at controller 40.
In many designs, this temporary increase in the xe2x80x9clowxe2x80x9d voltage level prevents signal receiving device 40 from properly interpreting the received signal.
The problem can theoretically be solved in a couple of different ways, each of which has its own disadvantages. One solution is to operate the bus at higher voltages (above VDSAT), thereby staying in the constant-current portion of the MOS transistor output. However, the fastest signal receiving devices often require low voltages to achieve their high speeds. Going to higher bus voltages would prevent the use of these relatively fast receiving devices.
Another approach is to lower the gate voltage of the drive transistor, and to use a bigger transistor. A lower gate voltage generally lowers VDSAT. However, using a bigger transistor raises the open-drain output capacitance of the driver device by a significant factor. This in turn affects the bus line impedance and the propagation velocity along the bus line. Furthermore, lowering the gate voltage severely increases its sensitivity to on-chip local noise. Dealing with this noise requires increased amounts of local bypassing of the gate voltage, increased power rails and/or additional Vss pins. Thus, this approach is often quite undesirable.
The inventors have found a way to provide nearly constant current from a MOS-based constant-current source, without resorting to either of the undesirable prior art solutions noted above. This allows higher bus speeds without the need to raise bus voltages or to use bigger drive transistors.
Described below is a current mode driver that provides constant output current at comparatively lower voltages than drivers of the prior art. In addition to a primary open-drain NMOS transistor, the described driver includes a supplemental current source that corrects for decreased output current from the primary transistor at low output voltages.
The supplemental current source comprises a voltage inverter and a current mirror. The voltage inverter produces a correction current that is inversely related to the output voltage of the primary transistor. The current mirror amplifies this current and supplies a supplemental current to the primary current generate by the primary transistor. The current mirror is self-limiting, to limit the supplemental current supplied by the supplemental current source.